Development Platform

Development PlatformProduct consists

  • HighTec's C/C++ multi-architecture and multi-core compiler suite with leading optimization technology
  • Support of architecture specific function blocks like GTM/MCS and HSM module
  • Eclipse IDE with extended project settings and graphical interface for linker description configuration


  • Eclipse Development EnvironmentMulti-core support (ISO and EABI compliant)
  • Long-term support and maintenance service
  • Latest optimization strategies
  • code compaction (reverse inlining)
  • global optimization strategies
  • Module-based grouping of data to minimize load address operation
  • Options per file and source code fragments
  • Optimized for Auto-Coding
  • Commercial standard and math libraries (no open source)
  • AUTOSAR MCAL driver support

Used by leading Tier1 and OEM

Advanced Multi-Core

  • Hide-and-visibility concept - interfaces between cores on linker level
  • The proprietary solution for migrating to multi-core
  • Application code can be ported to multi-core without source code modification
  • Proven software can be easily migrated to multi-core silicon
  • Based on linker level (ISO and EABI compliant) - a proprietary solution for migrating to multi-core
  • Core-ID information stored as meta-information on sections and in objects; easy extract info by analyzing symbol table
  • Support of homogenous and heterogeneous Multi-Core architectures


    • TriCoreAURIX 2G TC3xx, AURIX TC2xx and TriCore TC1xx
    • PCP-C, HSM and GTM/MCS compiler
    • SIMD and FPU support
    • Addressing modes: absolute, register relative, circular
    • Position Independent Code (PIC) and Data (PID)
    • Power ArchitectureQualcomm/NXP/Freescale - Qorivva MPC56xx, MPC57xx, MPC58xx
    • STMicroelectronics SPC56x, SPC57x, SPC58x
    • VLE, SPE and LSP support
    • Small Data Pointer functionality: about 20% code and run-time improvement
    • SIMD and FPU support
    • GTM/MCS support
    • Position Independent Code (PIC) and Data (PID)
    • RH850High-speed floating-point unit (FPU)
    • Inter-procedural optimizations
    • Multiple-Memory Models: Normal data, Small data, Zero data and tiny data
    • ARMNew: support of Cortex R52/Cortex A53
    • Thumb2 instruction set
    • VFP support
    • Cortex M3/M4 support

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